The present invention relates generally to electrically alterable read only memory arrays (EAROM) and more specifically to an amorphous memory array using emitter follower configured bipolar transistors.
The present state-of the-art of monolithic devices in amorphous technologies is limited to devices whose threshold voltages are very high, namely in the 10-20 volt range. This limitation arises from the desire to obtain devices with threshold characteristics which are suitable for high temperature operation. In programmable memory devices this limitation restricts the type of memory element which may be employed in the memory array. Prior techniques have utilized diodes and PNP transistors as the memory element in order to accommodate the high voltage necessary for switching of the amorphous elements. The use of diodes and PNP transistors requires that the matrix devices be isolated, and, hence restricts the memory array size.
The use of diodes and PNP emitter followers is described in U.S. Pat. No. 3,699,543 to Neale issued Oct. 17, 1972. The use of diodes, FET and bipolar transistors is discussed on pages 19-32 of thesis of C. H. Sie entitled "Memory Cell Using Bistable Resistivity in Amorphous As-Te-Ge Film" Iowa State University, May 1969.
A schematic and topological representation of an integrated circuit of a diode array and PNP emitter follower array of the prior art and the NPN emitter follower array of the present invention are illustrated in FIGS. 1 and 4, 2 and 5, and 3 and 6 respectively. Diodes D.sub.1, D.sub.2, D.sub.3 and D.sub.4 and transistors Q.sub.1, Q.sub.2, Q.sub.3 and Q.sub.4 each isolate amorphous storage devices S.sub.1, S.sub.2, S.sub.3 and S.sub.4 respectively. Lines A and F represent row select or word lines and lines C and E represent column select or bit lines.
As illustrated in FIG. 4, each of the diodes D.sub.1, D.sub.2, D.sub.3, D.sub.4 and respective storage devices S.sub.1, S.sub.2, S.sub.3, S.sub.4 are surrounded by junction isolation P.sup.++. A single cell has a width of ten units and a length of 20 units resulting in a surface area of 200 units. The PNP emitter follow of FIG. 5 requires a high impurity P.sup.++ region to junction isolate the rows of common bases. By using a common N-type base region for a row, the lateral isolation between the cells in a row is eliminated and a cell width of eighteen units compared to twenty units is possible. The cell length is seventeen units resulting in a surface area of 306 units. The NPN emitter follower of the present invention requires no isolation and is illustrated in FIG. 6 having a cell width of six units and length of eighteen units resulting in a surface area of 108 units. Thus, the electrical isolation requirements of diodes and PNP transistors increase the surface area used per cell.
By utilizing amorphous materials which have significantly improved temperature characteristics, lower switching threshold devices may be used-in the range of four to seven volts. These lower threshold devices then permit the use of NPN emitter follower devices as isolating elements in the memory array. Since an array of emitter follower devices with all collectors connected together does not require any isolation, the achievable memory array size is significantly increased. Diodes and PNP transistors were previously used with high switching threshold amorphous devices because of their high reverse breakdown voltage.